H03K19/17728- Reconfigurable logic blocks, e.g.H03K19/17724- Structural details of logic blocks.H03K19/1737- Controllable logic circuits using multiplexers.H03K19/1733- Controllable logic circuits.H03K19/1778- Structural details for adapting physical parameters.having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components having at least two inputs acting on one output Inverting circuits using specified components having at least two inputs acting on one output Inverting circuits Status Active legal-status Critical Current Adjusted expiration legal-status Critical Links LTD., LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MADURAWE, RAMINDA U Priority to US11/985,830 priority patent/US7466163B2/en Priority to US12/480,213 priority patent/US7656190B2/en Assigned to TIER LOGIC, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Publication of US20050146352A1 publication Critical patent/US20050146352A1/en Priority to US11/350,628 priority patent/US7208976B2/en Priority to US11/355,931 priority patent/US7176716B2/en Publication of US7019557B2 publication Critical patent/US7019557B2/en Application granted granted Critical Priority to US11/546,681 priority patent/US7239175B2/en Priority to US11/707,187 priority patent/US7285984B2/en Priority to US11/728,839 priority patent/US7336097B2/en Assigned to VICICIV TECHNOLOGY, INC. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Priority to US10/743,894 priority Critical patent/US7019557B2/en Application filed by Madurawe Raminda U. Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Raminda Madurawe Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US10/743,894 Other versions US7019557B2 Google Patents US20050146352A1 - Look-up table based logic macro-cells US20050146352A1 - Look-up table based logic macro-cells
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